As is known, the evolution of the electrical features of the processors for PCs, workstations and servers obliges manufacturers to find new solutions to meet the requirements demanded by central processing units (or CPUs).
In particular, CPUs of the new generation require high precision in their supply voltage, equal for example to +/−0.8% in the steady state and +/−3% in the transient state.
Next to these requirements for precision, the supply voltages that are used decrease to 1.1 V and the load currents rise to 130 A with edges of 100 A/μs, with a requirement for efficiency higher than 80%.
Therefore, suitable current or voltage controller devices must be used, which are able to ensure the efficiency required. A controller device suitable for CPU applications comprises for example a converter of the DC-DC interleaving type, used as an economic and efficient solution to meet the above needs and obtained by connecting, in parallel, N DC-DC converters in a Buck or Step-down configuration (i.e., by connecting their input and output terminals to each other driven in interleaved mode).
A known converter of the DC-DC interleaving type is shown in FIG. 1A. The converter 1 comprises a controller 2 connected to a plurality of n buffers or phases 3 (multiphase configuration) essentially comprising pairs of switches (High Side and Low Side), driven by the controller 2 so as to supply the required power to a CPU 4, which is connected to the output terminal OUT of the converter 1.
The interleaving driving of the converter 1 also implies that the controller 2 turns on the High Side switches of the n phases with a phase shift equal to the switch period T divided by the number n of phases.
A multiphase interleaving converter 1 is shown in greater detail in FIG. 1B. In particular, the converter 1 comprises n phases (indicated in the figure by their inductors L1 to Ln), with each phase 3 comprising a High Side switch SWhs connected in series to a Low Side switch SWls between a first and a second voltage reference, in particular an input voltage Vin and ground GND.
Each phase 3 also comprises an inductor L connected to a switch node X, or phase node that is between the switches SWhs and SWls. The converter 1 also comprises an output capacitor Cout inserted between the output terminal OUT and ground GND. Across the capacitor Cout there is an output voltage value Vout which is applied to the CPU 4.
The controller 2 supplies a driving signal of the PWM type for the High Side SWhs and Low Side SWls switches of the phases 3, which are sensitive to the level of the signal PWM. In particular, the High Side switches and the Low Side switches are respectively on and off if PWM=1, and the High Side switches and the Low Side switches are off and on respectively if PWM=0. To achieve this, the controller 2 comprises a suitable modulator 5.
In recent years, processors have been required to have their current specifications summarized in the underlying type of table.
TABLE 12004A2004B2004C2005A2005B2006AIMAX78A119A112A100A125A65AISTEP55A95A89A65A95A40A/60 AIstep/Trise69A/ms119A/ms111A/ms217A/ms317A/ms1200A/msIDCmin5A5A5A5A5A5AITDC68A101A96A85A115A56AI_RISE800nsec800nsecTBD/04_A310nsec310nsec50nsec
It should be noted that the increase in the required maximum currents (IMAX) stopped in 2005 and a decrease is foreseen in 2006 passing from about 125 A to 65 A. Such a decrease in the required maximum current would lead towards converter designs using a lower number of phases with respect to the preceding years.
In parallel, a very strong increase in the current demand rate of the processors (Istep/Irise) occurs, which greatly complicates the design of the DC-DC interleaving converters: the rate value Istep/Irise passes in fact from 69 A/ms (value in 2004) to the foreseen value of 1200 A/ms in 2006.
In other words, DC-DC interleaving converters of the next generation are required to meet more and more sudden load changes (or Load Transients). This need is also present in the case of a fast releasing of a load.
All this implies an increase in the costs of these converters for which the number of output capacitors Cout and thus the number n of phases of the converter itself is to be increased to respect the required voltage tolerances.
In particular, if up to now the number n of phases has been selected on the basis of efficiency, temperature of the components (i.e., reliability) and power density requirements, in the following years the number of phases will be established also on the basis of the required current speed specifications to be achieved.
Increasing the number of phases is in fact a way to increase the response speed of the converter to load requirements, in particular to sudden decreases of such requirements when the load is released.
Clearly, in the case of current changes equal to 70 A in a range of 50 ns, only an adequate number of ceramic capacitors can limit the voltage fall of the processor in the first 50 ns of the load transient.
In fact, the regulator has a band, which is proportional to n×Fsw, with n being the number of phases of the converter and Fsw being the switching frequency, in general about 300 kHz. Thus, there are obtained response times which are in inversely proportional to the band (for example, for n=4 a response time of about 800 ns is obtained).
The converter and its response speed can thus heavily influence its manufacturing cost and the number of electrolytic capacitors to be used (which influence the output voltage fall for the processor over longer times than for the ceramic capacitors).
Further, the band and response speed of the converter are however two indexes that no longer function for load transients as short as 50 ns, which cannot be considered a “small signal” shifting any more since the reaction times of the closed loop system (i.e., the band) are greater by at least one order of magnitude.
The known solutions aim at improving the response times of the controller without for this reason influencing its band.
An example of this known type of solution is shown in FIG. 2.
The controller 20 has a terminal OUT for its connection with a CPU, whereon there is a voltage signal Vout. The terminal OUT is connected to a first inner terminal FB by a resistor Rfb, and an error amplifier EA has a first input terminal, in particular an inverting one, connected to the first inner terminal FB as well as to a first current generator Gdroop for supplying this first input terminal of the error amplifier EA with a voltage value Idroop equal to K*ITOT, with K being a suitable scale factor and ITOT being a total current value flowing in the inductors of the phases of the converter to which the controller 20 is connected.
The error amplifier EA has a second input terminal, in particular a non-inverting one, that receives a reference voltage Ref, as well as an output terminal connected to a second inner terminal COMP of the controller 20, which is, in turn, feedback connected to the first inner terminal FB by the series made of a resistor Rf and of a capacitor Cf.
The second inner terminal COMP is connected to a plurality of control modules 21, in parallel to each other, and each having an output terminal 0 connected to a phase of the converter.
In particular, each control module 21 is inserted between a first and a second voltage reference, in particular a supply voltage Vdd and ground GND, and is connected to the second inner terminal COMP.
A generic control module 21 comprises a resistor Rs and a capacitor Cs, which are inserted in parallel between the second inner terminal COMP and an inner node Y of the control module, which is, in turn, connected to ground GND by a biasing generator Gp, which supplies a current value equal to K*IL, where K is the scale factor and IL is a value of the current flowing in the inductor L of the phase that is connected to the control module 21.
The control module 21 also comprises an input generator Gi, which is inserted between the supply voltage reference Vdd and the inner node Y, and is suitable for supplying a current value equal to K*IAVG, where K is the scale factor and IAVG is a mean value of the currents flowing in the inductors L of the phases of the converter.
The inner node Y is also connected to a first input terminal, in particular a non-inverting one, of an operational amplifier OA of the control module 21, which also has a second input terminal, in particular an inverting one, which receives a ramp signal RAMP (having frequency Fsw), and an output terminal 0, which is connected to a corresponding phase of the converter and supplies this phase with a driving signal PWM.
To improve the response time of the controller 20 without modifying its band, a supplemental capacitor Cd is inserted between the first inner terminal FB and the terminal OUT, in parallel to the resistor Rfb.
In this way, when there is a particularly quick Load Transient, this supplemental capacitor Cd becomes a much smaller impedance than the resistor Rfb resulting in the voltage value at the first inner terminal FB being no longer latched at a value equal to the reference voltage Ref (virtual ground due to the gain of the error amplifier EA) but it is dragged by the voltage signal Vout at the terminal OUT of the controller 20. The output terminal of the error amplifier EA, corresponding to the second inner terminal COMP, thus suddenly rises upwards with a speed proportional to the parameter GBWP (Gain Bandwidth Product) of the error amplifier EA and it saturates beyond the height of the driving signals PWM produced by the control modules 21.
In FIG. 2, the index j indicates the different phases of the converter connected to the controller 20, which, as previously described, comprise a High Side switch SWhs, inserted between an input voltage Vin and a switch node X (or phase node), and a Low Side switch SWls, inserted between the phase node X and ground GND, as well as an inductor L, inserted between the phase node X and the terminal OUT of the converter 1 whereon there is an output voltage value Vout, as well as a capacitor Cout inserted between the terminal OUT and ground GND.
The driving signals PWM set the turn on and off times of the switches SWhs and SWls. In particular, when the driving signal PWM is at a high value, or “1”, then the High Side switch SWhs is closed and the Low Side switch SWls is open. In a dual way, if the driving signal PWM is at a low value, or “0”, then the High Side switch SWhs is open and the Low Side switch SWls is closed.
Thanks to the configuration of the controller 20 shown in FIG. 2, the current IL flowing in each inductor L of each phase of the converter is read by the controller 20 through the scale factor K.
Although advantageous under several aspects, this known solution shows two important problems.
1) Even if the controller 20 realizes a sudden and quick movement of the inner terminal COMP (further to a Load Transient), each phase responds in reality only marginally to this Load Transient and does not completely contribute to sustain the voltage value Vout required at output due to the presence of the interleaving phase shifts of the phases themselves.
2) The speed with which the inner terminal COMP moves (a function of the parameter GBWP of the error amplifier EA) influences the speed at which the phases driven by the controller 20 are turned on or turned on again further to a Load Transient.
The first problem can be immediately linked to the choice of the time constant of the controller 20, which is equal to Cd*Rfp where:                the value of the resistor Rfb is chosen so as to program a desired droop effect, i.e., a departure of the voltage signal Vout from a value of the reference given by K*IToT*Rfb, with K being generally chosen so as to determine a maximum possible value of supplied current; and        the value of the supplemental capacitor Cd is chosen as high as possible so as to reduce the impedance of the parallel connection between itself and the resistor Rfb in the case of a Load Transient.        
However if the value of the supplemental capacitor Cd is too high, its derivative action also occurs in the steady state, i.e., in the absence of a Load Transient, by substantially amplifying the ripple of the voltage Vout (which is a signal with a value equal to about 10 mV and recurring at frequency n*Fsw, with n being the number of phases of the converter). If this occurs, the converter becomes unstable.
In other words, for a correct operation of the controller 20 the following relation is always to be respected.1/2πRfb*Cd>n*Fsw 
where Rd is the resistance value of the resistor Rd, Cd is the capacitance value of the capacitor Cd, and n*Fsw is the frequency of the signal Vout.
All this limits the movement of the inner terminal COMP for which each phase with a driving signal PWM higher than a control voltage in the instant when there is a Load Transient is only marginally turned on, as shown in FIG. 3.
In particular, this figure shows that the current of the inductor of the phase F4 is only marginally interested by the Load Transient, so only three phases out of four contribute to the rise of the output voltage value Vout. This situation is valid in a general way: only n−1 phases respond to a current change associated with a Load Transient, with at least one phase remaining “lazy”.
The second problem is instead associated with the repeatability of the parameter GBWP of the error amplifier EA of the controller 20. It is known that this parameter GBWP depends on a great number of technological parameters such as oxide thickness, lithographic tolerances, diffusivity of dopants, etc. Apart from the variance with the junction temperature, a departure of at least +/−50% from a nominal value of the parameter GBWP of an amplifier is a realistic situation.
Thus, considering an error amplifier EA with nominal GBWP of 30 MHz (which corresponds to a value of A0 equal to 100 dB and to a pole at 300 Hz), practically, the value of the parameter GBWP could vary between 15 MHz and 45 MHz.
By repeating the simulations on the known controller 20 with error amplifiers EA having the two extreme values indicated above for the parameter GBWP, the patterns shown in FIGS. 4A and 4B, respectively, are obtained, which highlight the dependency of the change of the output voltage Vout on the real value of the parameter GBWP of the error amplifier EA.
It thus occurs that, if for GBWP=45 MHz three phases out of four respond to the Load Transient, for GBWP=15 MHz, only two phases out of four respond to the same Load Transient. Thus the fall value of the output voltage Vout of the converter passes from 110 mV (with GBWP of 45 MHz) to 125 mV (with GBWP of 15 MHz).
Moreover, this known solution has no control during the load release step and is not able to “follow” sudden decreases of the current requirements under these release conditions with the production of undesired overshoots of the output voltage value.
To try and solve this problem, a technique called “body-brake” has been recently proposed which is used in the case of the release of the load and is described in U.S. Pat. No. 6,806,689. A method for controlling a converter of the multiphase interleaving type using the body-brake technique provides that under load release conditions, all the High Side and Low Side switches are turned off (while traditionally, i.e., in the case of controllers which do not use this body-brake technique, the controller would turn off the High Side switches but would turn on the Low Side switches SWls).
In this way the overshoot of the output voltage Vout after the load release is greatly decreased with respect to controllers which do not use this body-brake technique. In fact, the excess of charge dQ generated by the cancellation of the currents of the inductors L of the multiphase interleaving converter phases is decreased thanks to the presence of Low Side switches that are off.
In particular, in the case in which traditional controllers are used, this charge excess is equal to the following.dQ=L/Vout*Ipeak
Ipeak being a value of residual current in the inductances L of the converter phases, the voltage fall across these inductors L is equal to the output voltage Vout.
On the contrary, by using the body-brake technique, the voltage fall across the inductors L is equal to Vout+Vdiode, with Vdiode being the voltage value across the intrinsic diode of the Low Side switches under the off condition.
Thus, the fall across the inductors L is decreased thanks to the voltage fall on these intrinsic diodes and the charge excess is given by the following.dQ=L/(Vout+Vdiode)*Ipeak.
Thanks to this decrease of the charge excess dQ, a decrease of the overshoot of the output voltage Vout is obtained.
The on and off conditions of the Low Side switches are shown in FIGS. 4A and 4B, and the corresponding patterns of the current values in the inductors of the phases and the output voltage are qualitatively shown in FIGS. 4C-4E.
In particular, it is known to detect the load release condition by comparing a control voltage Vcntr (corresponding to an output voltage value of the error amplifier EA, i.e., the voltage value COMP) with a reference voltage Vr as well as with a clamping voltage Vclamp of the body-brake.
Normally, the reference voltage Vr has a ramp or sawtooth periodical wave form, as shown in FIG. 4E. The turn-on (ON) and the turn-off (OFF) of the High Side and Low Side switches is then decided according to the following rules.
If Vctr>Vr then High Side ON and Low Side OFF;
if Vctr<Vr and Vcntr>Vclamp then High Side OFF and Low Side ON; and
if Vctr<Vr and Vcntr<Vclamp then High Side OFF and Low Side OFF, this latter condition corresponding to the body-brake technique.